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features ? single 2.7v - 3.6v supply ? dual-interface architecture ? rapids serial interface: 66 mhz maximum clock frequency spi compatible modes 0 and 3 ? rapid8 8-bit interface: 50m hz maximum clock frequency ? user configurable page size ? 1024-bytes per page ? 1056-bytes per page ? page size can be factory pre-configured for 1024-bytes ? page program operation ? intelligent programming operation ? 8192 pages (1024-/1056-bytes/page) main memory ? flexible erase options ? page erase (1-kbyte) ? block erase (8-kbytes) ? sector erase (256-kbytes) ? chip erase (64mbits) ? two sram data buffers (1024-/1056-bytes) ? allows receiving of data whil e reprogramming the flash array ? continuous read capability through entire array ? ideal for code shadowing applications ? low-power dissipation ? 10ma active read current typical ? serial interface ? 10ma active read current typical ? 8-bit interface ? 25a standby current typical ? 15a deep power down typical ? hardware and software data protection features ? individual sector ? permanent sector lockdown for secure code and data storage ? individual sector ? security: 128-byte security register ? 64-byte user programmable space ? unique 64-byte device identifier ? jedec standard manufacturer and device id read ? 100,000 program/erase cycles per page minimum ? data retention ? 20 years ? green (pb/halide-free/rohs compliant) packaging options ? temperature range ? industrial: -40 ? c to +85 ? c 64-megabit 2.7v dual-interface dataflash at45db642d (not recommended for new designs) 3542n?dflash?2/2014
2 3542n?dflash?2/2014 at45db642d 1. description at45db642d is a 2.7v, dual-interface sequential access flash memory id eally suited for a wide variety of digital voice-, image-, program code- and data-storage applications. at45db642d supports rapids ? serial interface and rapid8 ? 8-bit interface. rapids serial interface is spi compatible for frequencies up to 66mhz. the dual-interface allows a dedicated serial interface to be connected to a dsp and a dedicated 8-bit in terface to be connected to a microcontroller or vice versa. however, the use of either interface is purely op tional. its 69,206,016-bits of memory are organized as 8,192 pages of 1,024-bytes (b inary page size) or 1,056-bytes (standard data- flash ? page size) each. in addition to the main memory, the at45db642d also contains two sram buffers of 1,024-(binary buffer size) byte s/1,056-bytes (standard dataflash buffer size) each. the buffers allow receiv ing of data while a page in the main memory is being repro- grammed, as well as writing a continuous da ta stream. eeprom emulation (bit or byte alterability) is easily handled with a self-contai ned three step re ad-modify-write operation. unlike conventional flash memories that are accessed ra ndomly with multiple address lines and a par- allel interface, the dataflash uses either a rapi ds serial interface or a 8-bit rapid8 interface to sequentially access its data. the simple sequent ial access dramatically reduces active pin count, facilitates hardware layout, increases syst em reliability, minimizes switching noise, and reduces package size. the device is optimized fo r use in many commercial and industrial appli- cations where high-density, low-pin count, low-voltage and low-po wer are essential. to allow for simple in-system reprogrammabi lity, the at45db642d does not require high input voltages for programming. the device operates from a single power supply, 2.7v to 3.6v, for both the program and read operations. the at45db 642d is enabled through the chip select pin (cs ) and accessed via a three-wire interface consisting of the serial input (si), serial output (so), and the serial clock (sck), or an 8-bit inte rface consisting of the input/output pins (i/o7 - i/o0) and the clock pin (clk). all programming and erase cycles are self-timed.
3 3542n?dflash?2/2014 at45db642d 2. pin configurations and pinouts table 2-1. pin configurations symbol name and function asserted state type cs chip select: asserting the cs pin selects the device. when the cs pin is deasserted, the device will be deselected and normally be placed in the standby mode (not deep power-down mode), and the output pins (so or i/o7 - i/o0) will be in a high-impedance state. when the device is deselected, data will not be accepted on the input pins (si or i/o7 - i/o0). a high-to-low transition on the cs pin is required to start an operation, and a low-to-high transition is required to end an o peration. when ending an internal ly self-timed operation such as a program or erase cycle, the device will not ente r the standby mode until the completion of the operation. low input sck/clk serial clock: this pin is used to provide a clock to the device and is used to control the flow of data to and from the device. command, address, an d input data present on the si or i/o7 - i/o0 pins are always latched on the rising edge of sc k/clk, while output data on the so or i/o7 - i/o0 pins are always clocked out on the falling edge of sck/clk. ? input si serial input: the si pin is used to shift data into the device. the si pin is used for all data input including command and address sequences. data on the si pin is always latched on the rising edge of sck. if the ser/byte pin is always driven low, the si pin should be a ?no connect?. ? input so serial output: the so pin is used to shift data out from the device. data on the so pin is always clocked out on the falling edge of sck. if the ser/byte pin is always driven low, the so pin should be a ?no connect?. ? output i/o7 - i/o0 8-bit input/output: the i/o7-i/o0 pins are bidirectional and used to clock data into and out of the device. the i/o7-i/o0 pins are used for all data input, including opcodes and address sequences. the use of these pins is optional, and the pins should be treated as ?no co nnect? if the ser/byte pin is not connected or if the ser/byte pin is always driven high externally. ? input/ output wp write protect: when the wp pin is asserted, all sectors specified for protection by the sector protection register will be protected against program and erase operations regardless of whether the enable sector protection co mmand has been issued or not. the wp pin functions independently of the software controlled protection method. if a program or erase command is issued to the device while the wp pin is asserted, the device will simply ignore the command and perform no opera tion. the device will return to the idle state once the cs pin has been deasserted. the enable sect or protection command and sector lockdown command, however, will be recognized by the device when the wp pin is asserted. the wp pin is internally pulled-high and may be left floating if hardware controlled protection will not be used. however, it is recommended that the wp pin also be externally connected to v cc whenever possible. low input reset reset: a low state on the reset pin (reset ) will terminate the operation in progress and reset the internal state machine to an idle state. the de vice will remain in the reset condition as long as a low level is present on the reset pin. normal operation can resume once the reset pin is brought back to a high level. the device incorporates an internal power-on reset circuit, so there are no restrictions on the reset pin during power-on sequences. if this pin a nd feature are not utilized it is recommended that the reset pin be driven high externally. low input rdy/busy ready/busy: this open drain output pin will be driven low when the device is busy in an internally self-timed operation. th is pin, which is normally in a high state (through an external pull-up resistor), will be pulled low during prog ramming/erase operations , compare operations, and page-to-buffer transfers. the busy status indicates that the flash memo ry array and one of the buffers cannot be accessed; read and write operations to the other buffer can still be performed. ? output
4 3542n?dflash?2/2014 at45db642d ser/byte serial/8-bit interface control: the dataflash may be configured to utilize either its serial port or 8-bit port through the use of the serial/8-bit control pin (ser/byte ). when the ser/byte pin is held high, the serial port (si and so) of the data flash will be used for all data transfers, and the 8-bit port (i/o7 - i/o0) will be in a high impeda nce state. any data presented on the 8-bit port while ser/byte is held high will be ignored. when the ser/byte is held low, the 8-bit port will be used for all data transfers, and the so pin of the serial port will be in a high impedance state. while ser/byte is low, any data presented on the si pi n will be ignored. switching between the serial port and 8-bit port should only be done while the cs pin is high and the device is not busy in an internally self-timed operation. the ser/byte pin is internally pulled high; therefore, if the 8-bit port is never to be used, then connection of the ser/byte pin is not necessary. in addition, if the ser/byte pin is not connected or if the ser/byte pin is always driven high externa lly, then the 8-bit input/output pins (i/o7-i/o0), the vccp pin, and the gndp pin should be treated as ?no connect?. low input v cc device power supply: the v cc pin is used to supply the source voltage to the device. operations at invalid v cc voltages may produce spurious results and should not be attempted. ?power gnd ground: the ground reference for the power supply. gnd should be connected to the system ground. ? ground v ccp 8-bit port supply voltage: the v ccp pin is used to supply power for the 8-bit input/output pins (i/o7-i/o0). the v ccp pin needs to be used if the 8-bit port is to be utilized; however, this pin should be treated as ?no connect? if the ser/byte pin is not connected or if the ser/byte pin is always driven high externally. ?power gndp 8-bit port ground: the gndp pin is used to provide grou nd for the 8-bit input/output pins (i/o7- i/o0). the gndp pin needs to be used if the 8-bit port is to be utilized; however, this pin should be treated as ?no connect? if the ser/byte pin is not connected or if the ser/byte pin is always driven high externally. ? ground table 2-1. pin configurations (continued) symbol name and function asserted state type figure 2-1. tsop top view: type 1 figure 2-2. bga package ball- out (top view) figure 2-3. cason top view through package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 rdy/busy reset wp nc nc vcc gnd nc nc nc cs sck/clk si so nc nc i/o7 i/o6 i/o5 i/o4 vccp gndp i/o3 i/o2 i/o1 i/o0 ser/byte nc a b c d e 5 4 3 2 1 nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc vcc gnd sck cs rdy/bsy wp si so reset si sck reset cs so gnd vcc wp 8 7 6 5 1 2 3 4
5 3542n?dflash?2/2014 at45db642d 3. block diagram 4. memory array to provide optimal flexibility, t he memory array of the at45db642d is divided into three levels of granularity comprising of sector s, blocks, and pages. the ?memory architecture diagram? illus- trates the breakdown of each leve l and details the number of pa ges per sector and block. all program operations to the dataflash occur on a page by page basis. the erase operations can be performed at the chip, sector, block or page level. figure 4-1. memory architecture diagram flash memory array page (1024-/1056-bytes) buffer 2 (1024-/1056-bytes) buffer 1 (1024-/1056-bytes) i/o interface sck/clk cs reset vcc gnd rdy/busy ser/byte wp so si i/o7 - i/o0 sector 0a = 8 pages 8192/8,448 bytes sector 0b = 248 pages 253,952/261,888 bytes block = 8,192-/8,448-bytes 8 pages sector 0 sector 1 page = 1,024-/1,056-bytes page 0 page 1 page 6 page 7 page 8 page 9 page 8,190 page 8,190 block 0 page 14 page 15 page 16 page 17 page 18 block 1 sector architecture block architecture page architecture block 0 block 1 block 30 block 31 block 32 block 33 block 1022 block 1023 block 62 block 63 block 64 block 65 sector 2 sector 31 = 256 pages 262,144/270,336 bytes block 2 sector 1 = 256 pages 262,144/270,336 bytes sector 30 = 256 pages 262,144/270,336 bytes sector 2 = 256 pages 262,144/270,336 bytes
6 3542n?dflash?2/2014 at45db642d 5. device operation the device operation is controlled by instructions from the host processor. the list of instructions and their associated opcodes are contained in table 15-1 on page 28 through table 15-6 on page 31 . a valid instruction starts with the falling edge of cs followed by the appropriate 8-bit opcode and the desired buffer or main memory address location. while the cs pin is low, tog- gling the sck/clk pin controls the loading of th e opcode and the desired buffer or main memory address location through either the si (serial in put) pin or the 8-bit inpu t pins (i/o7 - i/o0). all instructions, addresses, and data are transfer red with the most significant bit (msb) first. buffer addressing for standard dataflash page size (1056-bytes) is referenced in the datasheet using the terminology bfa10 - bfa0 to denote t he 11 address bits required to designate a byte address within a buffer. main memory addressing is referenced using the terminology pa12 - pa0 and ba10 - ba0, where pa12 - pa0 denotes the 13 address bits required to designate a page address and ba10 - ba0 denotes the 11 addre ss bits required to designate a byte address within the page. for ?power of 2? binary page size (1024-bytes) the buffer addressing is referenced in the data- sheet using the conventional terminology bfa9 - bfa0 to denote the 10 address bits required to designate a byte address within a buffer. main memory addressing is referenced using the termi- nology a22 - a0. 6. read commands by specifying the appropriate opcode, data can be read from the main memory or from either one of the two sram data buffers. the dataflash supports rapids and rapid8 protocols for mode 0 and mode 3. please refer to the ?detaile d bit-level read timing? diagrams in this data- sheet for details on the clock cycle sequences for each mode. 6.1 continuous array read (leg acy command: e8h): up to 66mhz by supplying an initial starting address for the main memory array, the continuous array read command can be utilized to sequentially read a continuous stream of data from the device by simply providing a clock signal; no additional addressing information or control signals need to be provided. the dataflash incorporates an inte rnal address counter that will automatically increment on every clock cycle, allowing one continuous read operation without the need of additional address sequences. to perform a cont inuous read from the standard dataflash page size (1056-bytes), an opcode of e8h must be cl ocked into the device followed by three address bytes (which comprise the 24-bit page and byte address sequence) and a series of don?t care bytes (4-bytes if using the serial interface or 19-b ytes if using the 8-bit in terface). the first 13-bits (pa12 - pa0) of the 24-bit address sequence specify which page of the main memory array to read, and the last 11 bits (ba10 - ba0) of the 24-bit address sequence sp ecify the starting byte address within the page. to perform a continuous read from the binary page size (1024-bytes), the opcode (e8h) must be clocked into the dev ice followed by three address bytes and a series of don?t care bytes (4-bytes if using the serial in terface, or 19-bytes if using the 8-bit interface). the first 13 bits (a22 - a10) of the 24-bits sequence specify which page of the main memory array to read, and the last 10 bits (a9 - a0) of the 24-bits address sequence specify the starting byte address within the page. the don?t care by tes that follow the address bytes are needed to initialize the read operation. following the don?t care bytes, additional clock pulses on the sck/clk pin will result in data be ing output on either the so (ser ial output) pin or the eight out- put pins (i/o7- i/o0).
7 3542n?dflash?2/2014 at45db642d the cs pin must remain low during the loading of the opcode, the address bytes, the don?t care bytes, and the reading of data. when the end of a page in main memory is reached during a continuous array read, the devic e will continue reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). when the last bit (or byte if using the 8-bit interface mode) in the main memory array has been read, the device will continue reading back at the beginning of the first page of memory. as with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array. a low-to-high transition on the cs pin will terminate the read ope ration and tri- state the output pins (so or i/o7-i/o0). the maximum sck/clk frequency allowable for the continuous array read is defined by the f car1 specification. the continuous array read bypasses both data buf- fers and leaves the contents of the buffers unchanged. 6.2 continuous array read (high fr equency mode: 0bh): up to 66mhz this command can be used with the serial interface to read the main memory array sequentially in high speed mode for any clock frequency up to the maximum specified by f car1 . to perform a continuous read array with the page size set to 1056-bytes, the cs must first be asserted then an opcode 0bh must be clocked into the devic e followed by three address bytes and a dummy byte. the first 13 bits (pa12 - pa0) of the 24-b it address sequence specify which page of the main memory array to read, and the last 11 bi ts (ba10 - ba0) of the 24-bit address sequence specify the starting byte addre ss within the page. to perfo rm a continuous read with the page size set to 1024-bytes, the opcode, 0bh, must be clocked into the device followed by three address bytes (a22 - a0) and a dummy byte. follo wing the dummy byte, additional clock pulses on the sck pin will result in data bei ng output on the so (serial output) pin. the cs pin must remain low during the loading of the opcode, the addres s bytes, and the read- ing of data. when the end of a page in the main memory is reached during a continuous array read, the device will continue reading at the be ginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). when the last bit in the main me mory array has been read, the device will con- tinue reading back at the begi nning of the first page of memory. as with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array. a low-to -high transition on the cs pin will term inate the read operation and tri-state the output pin (so). the maxi mum sck frequency allowable for the continuous array read is defined by the f car1 specification. the continuous array read bypasses both data buffers and leaves the contents of the buffers unchanged. 6.3 continuous array read (low fr equency mode: 03h): up to 33mhz this command can be used with the serial interface to read the main memory array sequentially without a dummy byte up to maximum frequencies specified by f car2 . to perform a continuous read array with the page size set to 1056-bytes, the cs must first be asserted then an opcode, 03h, must be clocked into the device followed by three address bytes (which comprise the 24-bit page and byte address sequence). the first 13 bits (pa12 - pa0) of the 24-bit address sequence specify which page of the main memory array to read, and the last 11 bits (ba10 - ba0) of the 24-bit address sequence specify the starting byte address within the page. to perform a contin- uous read with the page size set to 1024-bytes, the opcode, 03h, must be clocked into the device followed by three address bytes (a22 - a0 ). following the address bytes, additional clock pulses on the sck pin will result in data be ing output on the so (serial output) pin.
8 3542n?dflash?2/2014 at45db642d the cs pin must remain low during the loading of the opcode, the addres s bytes, and the read- ing of data. when the end of a page in the main memory is reached during a continuous array read, the device will continue reading at the be ginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). when the last bit in the main me mory array has been read, the device will con- tinue reading back at the begi nning of the first page of memory. as with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array. a low-to -high transition on the cs pin will term inate the read operation and tri-state the output pin (so). the conti nuous array read bypasses both data buffers and leaves the contents of the buffers unchanged. 6.4 main memory page read a main memory page read allows the user to read data directly from any one of the 8,192 pages in the main memory, bypassing both of the data buffers and leaving the contents of the buffers unchanged. to start a page read from the standard dataflash page size (1056-bytes), an opcode of d2h must be clocked into the device followed by three address bytes (which comprise the 24-bit page and byte address sequence) and a se ries of don?t care bytes (4-bytes if using the serial interface or 19-bytes if using the 8-bit in terface). the first 13 bits (pa12 - pa0) of the 24-bit address sequence specify the page in main memory to be read, and the last 11 bits (ba10 - ba0) of the 24-bit address sequence specify the starting byte address wit hin that page. to start a page read from the binary page size (1024-bytes), the opcode d2h must be clocked into the device followed by three address bytes and a series of don?t care bytes (4-bytes if using the serial interface or 19-bytes if using the 8-bit interface). the first 13 bits (a22 - a10) of the 24-bits sequence specify which page of the main memory array to read, and the last 10 bits (a9 - a0) of the 24-bits address sequence specify the starti ng byte address within the page. the don?t care bytes that follow the address bytes are sent to initialize the read operation. following the don?t care bytes, additional pulses on sck/clk result in data being output on either the so (serial output) pin or the eight output pins (i/o7 - i/o0). the cs pin must remain low during the loading of the opcode, the address bytes, the don?t care bytes, and the reading of data. when the end of a page in main memory is reached, the device will continue reading back at the beginning of the same page. a low-to-high transition on the cs pin will terminate the read operation and tri-state the output pins (so or i/o7 - i/o0). the maximum sck/clk frequency allowable for the main memory page read is defined by the f sck specification. the main memory page read bypasses both data buffers and leaves the co ntents of the buffers unchanged. 6.5 buffer read the sram data buffers can be accessed independe ntly from the main me mory array, and utiliz- ing the buffer read command allows data to be sequentially read directly from the buffers. in serial mode, four opcodes, d4h or d1h for buffer 1 and d6h or d3h for buffer 2 can be used for the buffer read command. the use of each opcode depends on the maximum sck frequency that will be used to read data from the buffer. the d4h and d6h opcode can be used at any sck frequency up to the maximum specified by f car1 . the d1h and d3h opcode can be used for lower frequency read operations up to the maximum specified by f car2 . in 8-bit mode, two opcodes, 54h for buffer 1 and 56h for buffer 2 can be used for the buffer read command. the two opcodes, 54h and 56h, can be used at any sck frequency up to the maximum specified by f car1 . to perform a buffer read from the standard dataflash buffer (1056- bytes), the opcode must be clocked into the devic e followed by three address bytes comprised of 13 don?t care bits and 11 buffer address bits (bfa10 - bfa0). to perform a buffer read from the binary buffer (1024-bytes), the opcode must be clocked into the device followed by three address bytes comprised of 14 don?t care bits and 10 buffer address bits (bfa9 - bfa0).
9 3542n?dflash?2/2014 at45db642d following the address bytes, additional don?t care bytes (one byte if using the serial interface or two bytes if using the 8-bit interf ace) must be clocked in to init ialize the read operation. the cs pin must remain low during the loading of the opcode, the address bytes, the don?t care bytes, and the reading of data. when the end of a buffer is reached, t he device will continue reading back at the beginning of the buffer. a low-to-high transition on the cs pin will terminate the read operation and tri-state the output pins (so or i/o7 - i/o0). 7. program and erase commands 7.1 buffer write data can be clocked in from the input pins (si or i/o7 - i/o0) into either buffer 1 or buffer 2. to load data into the standard dataflash buffer (105 6-bytes), a 1-byte opcode, 84h for buffer 1 or 87h for buffer 2, must be clocked into the device, followed by three address bytes comprised of 13 don?t care bits and 11 buffer address bits (bfa10 - bfa0). the 11 buffer address bits specify the first byte in the buffer to be written. to load data into the binary buffers (1024 bytes each), a 1-byte opcode 84h for buffer 1 or 87h for buffer 2, must be clocked into the device, followed by three address bytes comprised of 14 don?t care bits and 10 buffer address bits (bfa9 - bfa0). the 10 buffer address bits specify the first byte in the buffer to be written. after the last address byte has been clocked into the device, data can then be clocked in on subsequent clock cycles. if the end of the data buffer is reached, the de vice will wrap around back to the beginning of the buffer. data will continue to be load ed into the buffer un til a low-to-high transi tion is detected on the cs pin. 7.2 buffer to main memory page program with built-in erase data written into either buffer 1 or buffer 2 can be programmed into the main memory. a 1-byte opcode, 83h for buffer 1 or 86h for buffer 2, must be clocked into the device. for the standard dataflash page size (1056-bytes), the opcode must be followed by three address bytes consist of 13 page address bits (pa12 - pa0) that specify the page in the main memory to be written and 11 don?t care bits. to perform a buffer to main memory page program with built-in erase for the binary page size (1024-bytes), the opcode 83h for buffer 1 or 86h for buffer 2, must be clocked into the device followed by three address bytes consisting of 13 page address bits (a22 - a10) that specify the page in the main memory to be written and 10 don?t care bits. when a low-to- high transition occurs on the cs pin, the part will first erase the selected page in main memory (the erased state is a logic 1) and then program the data stored in the buffer into the specified page in main memory. both the erase and the programming of the page are internally self-timed and should take place in a maximum time of t ep . during this time, the status register and the rdy/busy pin will indicate that the part is busy. 7.3 buffer to main memory page program without built-in erase a previously-erased page within main memory can be programmed with the contents of either buffer 1 or buffer 2. a 1-byte opcode, 88h for buff er 1 or 89h for buffer 2, must be clocked into the device. for the stan dard dataflash page size (1056-bytes), the opcode must be followed by three address bytes consist of 13 page address bi ts (pa12 - pa0) that specify the page in the main memory to be written and 11 don?t care bits. to perform a buffer to main memory page pro- gram without built-in erase for the binary page size (1024-bytes), the opcode 88h for buffer 1 or 89h for buffer 2, must be clocked into the device followed by three address bytes consist of 13-page address bits (a22 - a10) that specify the page in the main memory to be written and 10 don?t care bits. when a low-to-high transition occurs on the cs pin, the part will program the data stored in the buffer into the specified page in the main memory. it is necessary that the
10 3542n?dflash?2/2014 at45db642d page in main memory that is being programmed has been previously erased using one of the erase commands (page erase or block erase). the programming of the page is internally self- timed and should take place in a maximum time of t p . during this time, the status register and the rdy/busy pin will indicate that the part is busy. 7.4 page erase the page erase command can be used to individually erase any page in the main memory array allowing the buffer to main memory page program to be utilized at a later time. to perform a page erase in the standard dataflash page size (1056-bytes), an opcode of 81h must be loaded into the device, followed by three address bytes comprised of 13 page address bits (pa12 - pa0) that specify the page in the main memory to be erased and 11 don?t care bits. to perform a page erase in the binary page size ( 1024-bytes), the opcode 81h must be loaded into the device, followed by three address bytes c onsist of 13 page address bits (a22 - a10) that specify the page in the main memory to be erased and 10 don?t care bits. when a low-to-high transition occurs on the cs pin, the part will erase the selected page (the erased state is a logi- cal 1). the erase operation is internally self-t imed and should take place in a maximum time of t pe . during this time, the status register and the rdy/busy pin will indicate that the part is busy. 7.5 block erase a block of eight pages can be erased at one ti me. this command is useful when large amounts of data has to be written into the device. th is will avoid using mult iple page erase commands. to perform a block erase for the standard datafl ash page size (1056 bytes), an opcode of 50h must be loaded into the device, followed by th ree address bytes comprised of 10 page address bits (pa12 -pa3) and 14 don?t care bits. the 10 page address bits are used to specify which block of eight pages is to be erased. to perfor m a block erase for the binary page size (1024- bytes), the opcode 50h must be loaded into the device, followed by three address bytes consist- ing of 10 page address bits (a22 - a13) and 13 don?t care bits. the 10 page address bits are used to specify which block of eight pages is to be erased. when a low-to-high transition occurs on the cs pin, the part will erase the selected block of eight pages. the eras e operation is inter- nally self-timed and should take place in a maximum time of t be . during this time, the status register and the rdy/busy pin will indicate that the part is busy. table 7-1. block erase addressing pa12/ a22 pa11/ a21 pa10/ a20 pa9/ a19 pa8/ a18 pa7/ a17 pa6/ a16 pa5/ a15 pa4/ a14 pa3/ a13 pa2/ a12 pa1/ a11 pa0/ a10 block 0000000000xxx 0 0000000001xxx 1 0000000010xxx 2 0000000011xxx 3 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1111111100xxx1020 1111111101xxx1021 1111111110xxx1022 1111111111xxx1023
11 3542n?dflash?2/2014 at45db642d 7.6 sector erase the sector erase command can be used to individually erase any sector in the main memory. there are 32 sectors and only one sector can be erased at one time. to perform sector 0a or sector 0b erase for the standard dataflash page size (1056-bytes), an opcode of 7ch must be loaded into the device, followed by three address bytes comprised of 10 page address bits (pa12 - pa3) and 14 don?t care bits. to perform a sector 1-31 erase, the opcode 7ch must be loaded into the device, followed by three address bytes comprised of five page address bits (pa12 - pa8) and 19 don?t care bits. to perform se ctor 0a or sector 0b erase for the binary page size (1024-bytes), an opcode of 7ch must be loaded into the device, followed by three address bytes comprised of one don?t care bit and 10 page address bits (a22 - a13) and 13 don?t care bits. to perform a sector 1-31 erase, the opc ode 7ch must be loaded into the device, followed by three address bytes comprised of one don?t care bit and five page address bits (pa12 - pa8) and 18 don?t care bits. the page address bits are used to specify any valid address location within the sector which is to be erased. wh en a low-to-high transition occurs on the cs pin, the part will erase the selected sector. the erase operation is internally self-timed and should take place in a maximum time of t se . during this time, the status register and the rdy/busy pin will indicate that the part is busy. 7.7 chip erase (1) the entire main memory can be erased at one time by using the chip erase command. to execute the chip erase command, a 4-byte command sequence c7h, 94h, 80h and 9ah must be clocked into the device. since the entir e memory array is to be erased, no address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. after the last bit of the op code sequence has been clocked in, the cs pin can be deas- serted to start the erase process. the erase operation is internally self-timed and should take place in a time of t ce . during this time, the status register will indicate that the device is busy. the chip erase command w ill not affect sectors that are prot ected or locked down; the contents of those sectors will re main unchanged. only those sectors that are not prot ected or locked down will be erased. table 7-2. sector erase addressing pa12/ a22 pa11/ a21 pa10/ a20 pa9/ a19 pa8/ a18 pa7/ a17 pa6/ a16 pa5/ a15 pa4/ a14 pa3/ a13 pa2/ a12 pa1/ a11 pa0/ a10 sector 0000000000xxx 0a 0000000001xxx 0b 0 0 0 0 1xxxxxxxx 1 0 0 0 1 0xxxxxxxx 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 1 1 0 0xxxxxxxx 28 1 1 1 0 1xxxxxxxx 29 1 1 1 1 0xxxxxxxx 30 1 1 1 1 1xxxxxxxx 31
12 3542n?dflash?2/2014 at45db642d the wp pin can be asserted while the device is eras ing, but protection will not be activated until the internal erase cycle completes. table 7-3. chip erase command figure 7-1. chip erase note: 1. refer to the errata regarding chip erase on page 56 7.8 main memory page program through buffer this operation is a combination of the buffer write and buffer to main memory page program with built-in erase operations. data is first clocked into buffer 1 or buffer 2 from the input pins (si or i/o7-i/o0) and then programmed into a specified page in the main memory. to perform the main memory page program through buffer for the standard dataflash page size (1056-bytes), a 1-byte opcode, 82h for buffer 1 or 85h for buffer 2, must first be clocked into the device, fol- lowed by three address bytes. the address by tes are comprised of 13 page address bits, (pa12-pa0) that select the page in the main memo ry where data is to be written, and 11 buffer address bits (bfa10-bfa0) that select the first byte in the buffer to be written. to perform a main memory page program through buffer for the binary page size (1024-bytes), the opcode 82h for buffer 1 or 85h for buffer 2, must be clo cked into the device followed by three address bytes consisting of 13 page address bits (a22 - a10) that specify the page in the main memory to be written, and 10 buffer address bits (bfa9 - bfa0) that selects the fi rst byte in the buffer to be written. after all address bytes are clocked in , the part will take data from the input pins and store it in the specified data bu ffer. if the end of the buffer is reached, the device will wrap around back to the beginning of the buffer. when there is a low-to-high transition on the cs pin, the part will first erase the selected page in ma in memory to all 1s and then program the data stored in the buffer into that memory page. both the erase and the programming of the page are internally self-timed and should ta ke place in a maximum time of t ep . during this time, the status register and the rdy/busy pin will indicate that the part is busy. 8. sector protection two protection methods, hardware and software co ntrolled, are provided for protection against inadvertent or erroneous program and erase cycl es. the software controlled method relies on the use of software commands to enable and di sable sector protection while the hardware con- trolled method employs the use of the write protect (wp ) pin. the selection of which sectors that are to be protected or unpr otected against program and erase operations is specified in the nonvolatile sector protection regi ster. the status of whether or not sector protection has been enabled or disabled by either the software or the hardware controll ed methods can be deter- mined by checking th e status register. command byte 1 byte 2 byte 3 byte 4 chip erase c7h 94h 80h 9ah opcode byte 1 opcode byte 2 opcode byte 3 opcode byte 4 cs each transition represents 8 bits si
13 3542n?dflash?2/2014 at45db642d 8.1 software sector protection 8.1.1 enable sector protection command sectors specified for protection in the sector pr otection register can be protected from program and erase operations by issuing the enable sect or protection command. to enable the sector protection using the softwar e controlled method, the cs pin must first be asse rted as it would be with any other command. once the cs pin has been asserted, the appropriate 4-byte command sequence must be clocked in via the input pins (s i or i/o7-i/o0). after the last bit of the com- mand sequence has been clocked in, the cs pin must be deasserted after which the sector protection will be enabled. table 8-1. enable sector protection command figure 8-1. enable sector protection 8.1.2 disable sector protection command to disable the sector protection using the software controlled method, the cs pin must first be asserted as it would be with any other command. once the cs pin has been asserted, the appropriate 4-byte sequence for the disable sector protection command must be clocked in via the input pins (si or i/o7-i/o0). after the last bit of the command sequence has been clocked in, the cs pin must be deasserted after which the sector protection will be disabled. the wp pin must be in the deasserted state; otherwise, the disable sector protection command will be ignored. table 8-2. disenable sector protection command figure 8-2. disable sector protection command byte 1 byte 2 byte 3 byte 4 enable sector protection 3dh 2ah 7fh a9h opcode byte 1 opcode byte 2 opcode byte 3 opcode byte 4 cs each transition represents 8 bits si or io 7 - io 0 command byte 1 byte 2 byte 3 byte 4 disable sector protection 3dh 2ah 7fh 9ah opcode byte 1 opcode byte 2 opcode byte 3 opcode byte 4 cs each transition represents 8 bits si or io 7 - io 0
14 3542n?dflash?2/2014 at45db642d 8.1.3 various aspects about software controlled protection software controlled protection is useful in applications in which the wp pin is not or cannot be controlled by a host processor. in such instances, the wp pin may be left floating (the wp pin is internally pulled high) and sector protection ca n be controlled using the enable sector protection and disable sector protection commands. if the device is power cy cled, then the software controlled pr otection will be disabled. once the device is powered up, the enable sector protection command shoul d be reissued if sector pro- tection is desired and if the wp pin is not used. 9. hardware controlled protection sectors specified for protection in the sector pr otection register can be protected from program and erase operations by asserting the wp pin and keeping the pin in its asserted state. any sec- tor specified for protection cannot be erased or reprogrammed as long as the wp pin is asserted. the wp pin will override the software controlled protection method but only for protecting the sectors. for example, if the sectors were not pr eviously protected by t he enable sector protec- tion command, then simply asserting the wp pin would enable the sector protection within the maximum specified t wpe time. when the wp pin is deasserted; however, the sector protection would no longer be enabled (after the maximum specified t wpd time) as long as the enable sec- tor protection command was not issued while the wp pin was asserted. if the enable sector protection command was issued before or while the wp pin was asserted, then simply deassert- ing the wp pin would not disable the sector protection. in this case, the disable sector protection command would need to be issued while the wp pin is deasserted to disable the sec- tor protection. the disable se ctor protection command is also ignored whenever the wp pin is asserted. a noise filter is incorporated to help protect aga inst spurious noise that may inadvertently assert or deassert the wp pin. the table below details the sector protecti on status for various scenarios of the wp pin, the enable sector protection command, and the disable sector protection command. figure 9-1. wp pin and protection status wp 12 3 table 9-1. wp pin and protection status time period wp pin enable sector protection command disable sector protection command sector protection status 1high command not issued previously ? issue command x issue command ? disabled disabled enabled 2 low x x enabled 3high command issued during period 1 or 2 ? issue command not issued yet issue command ? enabled disabled enabled
15 3542n?dflash?2/2014 at45db642d 9.1 sector protection register the nonvolatile sector protection register specifies which sectors are to be protected or unpro- tected with either the software or hardware cont rolled protection methods. the sector protection register contains 32-bytes of data, of which by te locations 0 through 31 contain values that specify whether sectors 0 through 31 will be pr otected or unprotected. the sector protection register is user modifiable and must first be erased before it can be reprogrammed. table 9-3 illustrates the format of the sector protection register.: note: 1. the default value for bytes 0 through 31 when shipped from adesto ? is 00h x = don?t care 9.1.1 erase sector protection register command in order to modify and change the values of t he sector protection regi ster, it must first be erased using the erase sector protection register command. to erase the sector protection register, the cs pin must first be asse rted as it would be with any other command. once the cs pin has been asserted, the appropriate 4-byte opcode sequence must be clocked into the device via th e si or i/o7 - i/o0 pin. the 4-byte opcode sequence must start with 3dh and be followed by 2a h, 7fh, and cfh. after the last bit of the opcode sequence has been clocked in, the cs pin must be deasserted to initiate the internally self-timed erase cycle. the erasing of the sector protection register should take place in a time of t pe , during which time the status register will indica te that the device is busy. if the device is powered-down before the completion of the erase cycle, then the co ntents of the sector protec- tion register cannot be guaranteed. the sector protection register can be erased with the sector protection enabled or disabled. since the erased state (ffh) of each byte in the sector protection register is used to indicate that a sector is specified for protection, leaving the sector protection enabled during the erasing of the register allows the protection scheme to be more effective in th e prevention of accidental programming or erasing of the device. if for some reason an erroneous program or erase com- mand is sent to the device imm ediately after erasing the sector protection register and before the register can be reprogrammed, then the erroneous program or erase command will not be processed because all sectors would be protected. table 9-2. sector protection register sector number 0 (0a, 0b) 1 to 31 protected see table 9-3 ffh unprotected 00h table 9-3. sector 0 (0a, 0b) 0a 0b bit 3, 2 data value (page 0-7) (page 8-255) bit 7, 6 bit 5, 4 bit 1, 0 sectors 0a, 0b unprotected 00 00 xx xx 0xh protect sector 0a 11 00 xx xx cxh protect sector 0b (page 8-255) 00 11 xx xx 3xh protect sectors 0a (page 0-7), 0b (page 8-255) (1) 11 11 xx xx fxh
16 3542n?dflash?2/2014 at45db642d table 9-4. erase sector protection register command figure 9-2. erase sector protection register 9.1.2 program sector protection register command once the sector protection register has been erased, it can be reprogrammed using the pro- gram sector protecti on register command. to program the sector protection register, the cs pin must first be asserted and the appropri- ate 4-byte opcode sequence must be clocked into the device via the si or i/o7 - i/o0 pin. the 4- byte opcode sequence must start with 3dh and be followed by 2ah, 7fh, and fch. after the last bit of the opcode sequence has been clocked in to the device, the data for the contents of the sector protection register must be clocked in. as described in section 9.1 , the sector protec- tion register contains 32-bytes of data, so 32-by tes must be clocked into the device. the first byte of data corresponds to sector 0, the second byte corresponds to sector 1, and so on with the last byte of data corresponding to sector 31. after the last data byte has been clocked in, the cs pin must be deasserted to initiate the inter- nally self-timed program cycle. the programming of the sector protection register should take place in a time of t p , during which time the stat us register will indicate that the device is busy. if the device is powered-down during the program cyc le, then the contents of the sector protection register cannot be guaranteed. if the proper number of data bytes is not clocked in before the cs pin is deasserted, then the protection status of the sectors corresponding to the bytes not clocked in can not be guaranteed. for example, if only the first tw o bytes are clocked in instead of the complete 32-bytes, then the protection status of the last 30 sectors cannot be guaranteed. furthermore, if more than 32- bytes of data is clocked into th e device, then the data will wrap back around to the beginning of the register. for instance, if 33-byte s of data are clocked in, then the 33 rd byte will be stored at byte location 0 of the sector protection register. if a value other than 00h or ffh is clocked into a byte location of the sector protection register, then the protection status of the sector corresponding to that byte location cannot be guaran- teed. for example, if a value of 17h is clocked into byte location 2 of the sector protection register, then the protection status of sector 2 cannot be guaranteed. the sector protection register can be reprogramm ed while the sector prot ection enabled or dis- abled. being able to reprogram the sector protecti on register with the se ctor protection enabled allows the user to temporarily disable the sector pr otection to an individual sector rather than dis- abling sector protection completely. the program sector prot ection register command utilizes the internal sram bu ffer for process- ing. therefore, the contents of the buffer will be altered from its previous state when this command is issued. command byte 1 byte 2 byte 3 byte 4 erase sector protection register 3dh 2ah 7fh cfh opcode byte 1 opcode byte 2 opcode byte 3 opcode byte 4 cs each transition represents 8 bits si or io 7 - io 0
17 3542n?dflash?2/2014 at45db642d table 9-5. program sector protection register command figure 9-3. program sector protection register 9.1.3 read sector protection register command to read the sector protection register, the cs pin must first be asserted. once the cs pin has been asserted, an opcode of 32h and a series of dummy bytes (three dummy bytes if using the serial interface or seven dummy by tes if using the 8-bit interface) must be clocked in via the si or i/o7 or i/o0 pins. after the last bit of t he opcode and dummy bytes have been clocked in, any additional clock pulses on the sck/clk pins will re sult in data for the co ntent of the sector pro- tection register being output on the so or i/o7- i/o0 pins. the first byte corresponds to sector 0 (0a, 0b), the second byte corresponds to sector 1 and the last byte (byte 32) corresponds to sec- tor 31. once the last byte of the sector protecti on register has been cl ocked out, any additional clock pulses will result in undefined data being output on the so or i/o pins. the cs must be deasserted to terminate the read sector protection register oper ation and put the output into a high-impedance state. table 9-6. read sector protection register command note: xx = dummy byte serial interface = 3 du mmy bytes 8-bit interface = 7 dummy bytes figure 9-4. read sector protection register command byte 1 byte 2 byte 3 byte 4 program sector protection register 3dh 2ah 7fh fch data byte n opcode byte 1 opcode byte 2 opcode byte 3 opcode byte 4 data byte n + 1 data byte n + 31 cs each transition represents 8 bits si or io 7 - io 0 command byte 1 byte 2 byte 3 byte 4 read sector protecti on register 32h xxh xxh xxh opcode x x x data byte n data byte n + 1 cs data byte n + 31 si or io 7 - io 0 so or io 7 - io 0 each transition represents 8 bits
18 3542n?dflash?2/2014 at45db642d 9.1.4 various aspects about the sector protection register the sector protection register is subject to a limit of 10,000 erase/program cycles. users are encouraged to carefully evaluate the number of times the sector prot ection register will be modified during the course of the applications? life cycle. if the application requires that the sec- tor protection register be modi fied more than the specified lim it of 10,000 cycles because the application needs to temporarily unprotect indivi dual sectors (sector protection remains enabled while the sector protection regi ster is reprogrammed), then the application will need to limit this practice. instead, a combination of temporarily unprotecting individual sectors along with dis- abling sector protection completely will need to be implement ed by the applicatio n to ensure that the limit of 10,000 cycles is not exceeded. 10. security features 10.1 sector lockdown the device incorporates a sector lockdown mechan ism that allows each individual sector to be permanently locked so that it becomes read only. th is is useful for applications that require the ability to permanently protect a nu mber of sectors against malicious attempts at altering program code or security information. once a sector is locked down, it can never be erased or pro- grammed, and it can never be unlocked. to issue the sector lockdown command, the cs pin must first be asserted as it would be for any other command. once the cs pin has been asserted, the appropriate 4-byte opcode sequence must be clocked into the device in the correct order. the 4-byte opcode sequence must start with 3dh and be followe d by 2ah, 7fh, and 30h. afte r the last byte of the command sequence has been clocked in, then three address bytes specifying any address within the sec- tor to be locked down must be clocked into the device. after the last address bit has been clocked in, the cs pin must then be deasserted to initia te the internally self-timed lockdown sequence. the lockdown sequence should take place in a maximum time of t p , during which time the status register will indicate that the device is busy. if the device is powered-down before the comple- tion of the lockdown sequence, then the lockdown st atus of the sector cannot be guaranteed. in this case, it is recommended that the user re ad the sector lockdown register to determine the status of the appropriate sector lockdown bits or bytes and reissue the sector lockdown com- mand if necessary. table 10-1. sector lockdown figure 10-1. sector lockdown command byte 1 byte 2 byte 3 byte 4 sector lockdown 3dh 2ah 7fh 30h opcode byte 1 opcode byte 2 opcode byte 3 opcode byte 4 cs address bytes address bytes address bytes each transition represents 8 bits si or io 7 - io 0
19 3542n?dflash?2/2014 at45db642d 10.1.1 sector lockdown register sector lockdown register is a nonvolatile regi ster that contains 32-bytes of data, as shown below: table 10-2. sector lockdown register 10.1.2 reading the sector lockdown register the sector lockdown register can be read to de termine which sectors in the memory array are permanently locked down. to read the sector lockdown register, the cs pin must first be asserted. once the cs pin has been asserted, an opcode of 35h and a series of dummy bytes (three dummy bytes if using the serial interface or seven dummy bytes if using the 8-bit inter- face) must be clocked into the device via the si or i/o7-o0 pi ns. after the last bit of the opcode and dummy bytes have been clocked in, the data for the contents of the sector lockdown reg- ister will be clocked out on the so pin or the i/o7 -o0 pins. the first byte corresponds to sector 0 (0a, 0b) the second byte corresponds to sector 1 and the las byte (byte 32) corresponds to sec- tor 31. after the last byte of the sector loc kdown register has been read, additional pulses on the sck pin will simply result in undefin ed data being output on the so pin. deasserting the cs pin will terminate the read sector lock down register operation and put the so pin or i/o7-o0 pins into a high-impedance state. table 10-4 details the values read from the sector lockdown register. figure 10-2. read sector lockdown register sector number 0 (0a, 0b) 1 to 31 locked see below ffh unlocked 00h table 10-3. sector 0 (0a, 0b) 0a 0b bit 3, 2 data value (page 0-7) (page 8-255) bit 7, 6 bit 5, 4 bit 1, 0 sectors 0a, 0b unlocked 00 00 00 00 00h sector 0a locked 11 00 00 00 c0h sector 0b locked (page 8-255) 00 11 00 00 30h sectors 0a, 0b locked (page 0-255) 11 11 00 00 f0h table 10-4. sector lockdown register command byte 1 byte 2 byte 3 byte 4 read sector lockdown register 35h xxh xxh xxh note: xx = dummy byte serial interface = 3 du mmy bytes 8-bit interface = 7 dummy bytes opcode x x x data byte n data byte n + 1 cs data byte n + 31 si or io 7 - io 0 so or io 7 - io 0 each transition represents 8 bits
20 3542n?dflash?2/2014 at45db642d 10.2 security register the device contains a specialized security r egister that can be used for purposes such as unique device serialization or lo cked key storage. the register is comprised of a total of 128- bytes that is divided into two portions. the fi rst 64-bytes (byte locations 0 through 63) of the security register are allocated as a one-time user programmable space. once these 64-bytes have been programmed, they cannot be reprog rammed. the remaining 64-bytes of the register (byte locations 64 through 127) are factory pr ogrammed by adesto and will contain a unique value for each device. the factory program med data is fixed and cannot be changed. 10.2.1 programming the security register the user programmable portion of the security regi ster does not need to be erased before it is programmed. to program the security register, the cs pin must first be asserted and the appropriate 4-byte opcode sequence must be clocked into the devic e in the correct order. the 4-byte opcode sequence must start with 9bh and be followed by 00 h, 00h, and 00h. after the last bit of the opcode sequence has been clocked into the device, the data for the contents of the 64-byte user programmable portion of the security register must be clocked in. after the last data byte has been clocked in, the cs pin must be deasserted to initiate the inter- nally self-timed program cycle. the programming of the security register should take place in a time of t p , during which time the status register will indi cate that the device is busy. if the device is powered-down during the program cycle, then the contents of the 64-byte user programmable portion of the security register cannot be guaranteed. if the full 64-bytes of data is not clocked in before the cs pin is deasserted, then the values of the byte locations not clocked in cannot be guaranteed. for example, if only the first two bytes are clocked in instead of the complete 64-bytes, then the remaining 62-bytes of the user pro- grammable portion of the security register cannot be guaranteed. furthermore, if more than 64- bytes of data is clocked into th e device, then the data will wrap back around to the beginning of the register. for instance, if 65-bytes of data are clocked in, then the 65 th byte will be stored at byte location zero of the security register. the user programmable portion of the security register can only be programmed one time. therefore, it is not possible to only program the first two bytes of the register and then pro- gram the remaining 62-bytes at a later time. the program security register command utiliz es the internal sram buffer for processing. therefore, the contents of the buffer will be altered from its previous state when this command is issued. figure 10-3. program security register table 10-5. security register security register byte number 01 ????? 62 63 64 65 ????? 126 127 data type one-time user programmable factory programmed by adesto data byte n opcode byte 1 opcode byte 2 opcode byte 3 opcode byte 4 data byte n + 1 data byte n + x cs each transition represents 8 bits si or io 7 - io 0
21 3542n?dflash?2/2014 at45db642d 10.2.2 reading the security register the security register can be read by first asserting the cs pin and then clocking in an opcode of 77h followed by three dummy bytes if using the serial interface and seven dummy bytes if using the 8-bit interface. after the last don't care bit has been clocked in, the content of the security register can be clocked out on the so or i/o7 - i/o0 pins. after the last byte of the security register has been read, additional pulse s on the sck/clk pin will simply result in undefined data being output on the so or i/o7 - i/o0 pins. deasserting the cs pin will terminate the r ead security register o peration and put the so or i/o7 - i/o0 pins into a high-impedance state. figure 10-4. read security register 11. additional commands 11.1 main memory page to buffer transfer a page of data can be transferred from the main memory to either buffer 1 or buffer 2. to start the operation for the standard dataflash page si ze (1056-bytes), a 1-byte opcode, 53h for buf- fer 1 and 55h for buffer 2, must be clocked into the device, followed by three address bytes comprised of 13 page address bits (pa12 - pa0), which specify the page in main memory that is to be transferred, and 11 don?t care bits. to perform a main memory page to buffer transfer for the binary page size (1024-bytes), the opcode 53h for buffer 1 or 55h for buffer 2, must be clocked into the device followed by three address bytes consisting of 13 page address bits (a22 - a10) which specify the page in the main memo ry that is to be transferred, and 10 don?t care bits. the cs pin must be low while toggling the sck/clk pin to load the opcode and the address bytes from the input pins (si or i/o7 - i/o0). the transfer of the page of data from the main memory to the bu ffer will begin when the cs pin transitions from a low to a high state. during the transfer of a page of data (t xfr ), the status register can be read or the rdy/busy can be monitored to determine whether the transfer has been completed. 11.2 main memory page to buffer compare a page of data in main memory can be compared to the data in buffer 1 or buffer 2. to initiate the operation for standard dataflash page size, a 1-byte opcode, 60h for buffer 1 and 61h for buffer 2, must be clocked into the device, follo wed by three address bytes consisting of 13 page address bits (pa12 - pa0) that specify the page in the main memory that is to be compared to the buffer, and 11 don?t care bits. to start a main memory page to buffer compare for a binary page size, the opcode 60h for buffer 1 or 61h for buf fer 2, must be clocked into the device fol- lowed by three address bytes consisting of 13 pa ge address bits (a22 - a10) that specify the page in the main memory that is to be compared to the buffer, and 10 don?t care bits. the cs pin must be low while toggling the sck/clk pin to load the opcode and the address bytes from the opcode x x x data byte n data byte n + 1 cs data byte n + x each transition represents 8 bits si or io 7 - io 0 so or io 7 - io 0
22 3542n?dflash?2/2014 at45db642d input pins (si or i/o7 - i/o0). on the low-to-high transition of the cs pin, the data bytes in the selected main memory page will be compared with the data bytes in buffer 1 or buffer 2. during this time (t comp ), the status regist er and the rdy/busy pin will indicate that the part is busy. on completion of the compare operation, bit 6 of the status register is updated with the result of the compare. 11.3 auto page rewrite this mode is only needed if mult iple bytes within a page or multiple pages of data are modified in a random fashion within a sector. this mode is a combination of two operations: main memory page to buffer transfer and buffer to main memory page program with built-in erase. a page of data is first transferred from the main memory to buffer 1 or buffer 2, and then the same data (from buffer 1 or buffer 2) is programmed back into its original page of main memory. to start the rewrite operation for standard dataflash page si ze (1056-bytes), a 1-byte opcode, 58h for buf- fer 1 or 59h for buffer 2, must be clocked in to the device, followed by three address bytes comprised of 13 page address bits (pa12-pa0) that specify the page in main memory to be rewritten and 11 don?t care bits. to initiate an auto page rewrite for a binary page size (1024- bytes), the opcode 58h for buffer 1 or 59h for buff er 2, must be clocked into the device followed by three address bytes consisting of 13 page address bits (a22 - a10) that specify the page in the main memory that is to be written and 10 don?t care bits. when a low-to-high transition occurs on the cs pin, the part will first transfer data fr om the page in main memory to a buffer and then program the data from the buffer back into same page of main memory. the operation is internally self-timed and should take place in a maximum time of t ep . during this time, the sta- tus register and the rdy/busy pin will indicate that the part is busy. if a sector is programmed or reprogrammed sequentially page by page, then the programming algorithm shown in figure 26-1 ( page 49 ) is recommended. otherwise , if multiple bytes in a page or several pages are programmed randomly in a sector, then the programming algorithm shown in figure 26-2 ( page 50 ) is recommended. each page within a sector must be updated/rewritten at least once within every 20,000 cumulative page erase/program operations in that sector. please contact adesto for availability of devices that are specified to exceed the 20k cycle cumulative limit. 11.4 status register read the status register can be used to determine the device?s ready/busy status, page size, a main memory page to buffer compare operation resul t, the sector protection status or the device density. to read the status regi ster, an opcode of d7h must be loaded into the device. after the opcode is clocked in, the 1-byte status regist er will be clocked out on the output pins (so or i/o7 - i/o0), starting with the next clock cycle. in ca se of applications with 8-bit interface, opcode d7h and two dummy clock cycles should be used. when using the serial interface, the data in the status register, starting wi th the msb (bit 7), will be clock ed out on the so pi n during the next eight clock cycles. after the one byte of the st atus register has been cl ocked out, the sequence will repeat itself (as long as cs remains low and sck/clk is being toggled). the data in the sta- tus register is cons tantly updated, so each repeati ng sequence will output new data. ready/busy status is indicated using bit seven of the status register. if bit seven is a one, then the device is not busy and is ready to accept th e next command. if bit seven is a zero, then the device is in a busy state. sinc e the data in the status register is constantly updated, the user must toggle sck/clk pin to check the ready/busy status. there are several operations that can cause the device to be in a busy state: main memory page to buffer transfer, main memory page to buffer compare, buffer to main memory page program, main memory page program through buffer, page erase, block erase, sect or erase, chip erase and auto page rewrite.
23 3542n?dflash?2/2014 at45db642d the result of the most recent main memory page to buffer compare operation is indicated using bit 6 of the status register. if bit six is a zero , then the data in the main memory page matches the data in the buffer. if bit six is a one, then at least one bit of the data in the main memory page does not match the data in the buffer. bit one in the status register is used to provid e information to the user whether or not the sector protection has been enabled or disabled, either by software-controlled method or hardware-con- trolled method. a logic 1 indicates that sector protection has been enabled and logic 0 indicates that sector protection has been disabled. bit zero in the status register indicates whether the page size of the main memory array is con- figured for ?power of 2? binary page size (1024-bytes) or standard dataflash page size (1056- bytes). if bit zero is a one, then the page size is se t to 1024-bytes. if bit ze ro is a zero , then the page size is set to 1056-bytes. the device density is indicated using bits five, f our, three, and two of the status register. for the at45db642d, the four bits are 1111 the decimal va lue of these four binary bits does not equate to the device density; the four bi ts represent a combinat ional code relating to differing densities of dataflash devices. the device density is not the same as t he density code indicated in the jedec device id information. the device densit y is provided only for backward compatibility. 12. deep power-down after initial powe r-up, the device will default in stand by mode. the deep power-down command allows the device to enter into the lowest power consumption mode. to enter the deep power- down mode, the cs pin must first be asserted. once the cs pin has been asserted, an opcode of b9h command must be clocked in via input pins (si or io 7 -io 0 ). after the last bit of the com- mand has been clocked in, the cs pin must be de-asserted to initiate the deep power-down operation. after the cs pin is de-asserted, the will device enter the deep power-down mode within the maximum t edpd time. once the device has enter ed the deep power-down mode, all instructions are ignored except for the resume from deep power-down command. table 12-1. deep power-down figure 12-1. deep power-down table 11-1. status register format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rdy/busy comp 1 1 1 1 protect page size command serial/8-bit opcode deep power-down both b9h opcode cs each transition represents 8 bits si or io 7 - io 0
24 3542n?dflash?2/2014 at45db642d 12.1 resume from deep power-down the resume from deep power-down command takes the device out of the deep power-down mode and returns it to the normal standby mode. to resume from deep power-down mode, the cs pin must first be asserted and an opcode of abh command must be clocked in via input pins (si or io 7 -io 0 ). after the last bit of the command has been clocked in, the cs pin must be de- asserted to terminate the deep power-down mode. after the cs pin is de-asserted, the device will return to the normal standby mode within the maximum t rdpd time. the cs pin must remain high during the t rdpd time before the device can receive any commands. after resuming form deep power-down, the de vice will return to th e normal standby mode. table 12-2. resume from deep power-down figure 12-2. resume from deep power-down 13. ?power of 2? binary page size option ?power of 2? binary page size configuration regi ster is a user-programmable nonvolatile regis- ter that allows the page size of the main me mory to be configured for binary page size (1024- bytes) or standard dataflash page size (1056-bytes). the ?power of 2? page size is a one- time programmable configuration register and once the device is configured for ?power of 2? page size, it cannot be reconfigured again. the devices are initially shipped with the page size set to 1056-bytes. the user has the option of ordering binary page size (1024- bytes) devices from the factory. for details, please refer to section 27. ?ordering information? on page 51 . for the binary ?power of 2? page size to becom e effective, the following steps must be followed: 1. program the one-time programmable configuration resister using opcode sequence 3dh, 2ah, 80h and a6h (please see section 13.1 ). 2. power cycle the device (i.e. power down and power up again). 3. user can now program the page for the binary page size. if the above steps are not followed in setting t he the page size prior to page programming, user may expect incorrect data during a read operation. command serial/8-bit opcode resume from deep power-down both abh opcode cs each transition represents 8 bits si or io 7 - io 0
25 3542n?dflash?2/2014 at45db642d 13.1 programming the c onfiguration register to program the configuration register fo r ?power of 2? binary page size, the cs pin must first be asserted as it would be with any other command. once the cs pin has been asserted, the appropriate 4-byte opcode sequence must be clocked into the device in the correct order. the 4- byte opcode sequence must start with 3dh and be followed by 2ah, 80h, and a6h. after the last bit of the opcode sequence has been clocked in, the cs pin must be deasserted to initiate the internally self-timed prog ram cycle. the programming of th e configuration register should take place in a time of t p , during which time the st atus register will indi cate that the device is busy. the device must be power-cycled after th e completion of the program cycle to set the ?power of 2? page size. if the device is powered-down before the completion of the program cycle, then setting the configur ation register cannot be guaranteed. however, the user should check bit 0 of the stat us register to see whether the page size was configured for binary page size. if not, the command can be re-issued again. table 13-1. programming the configuration register figure 13-1. erase sector protection register 14. manufacturer an d device id read identification information can be read from the dev ice to enable systems to electronically query and identify the device while it is in system. the identificati on method and the command opcode comply with the jedec standard for ?manufacturer and device id read methodology for spi compatible serial interf ace memory devices?. the type of information that can be read from the device includes the jedec defined manufacturer id, the vendor specific device id, and the ven- dor specific extended device information. to read the identification information, the cs pin must first be asserted and the opcode of 9fh must be clocked into the device. after the opc ode has been clocked in, the device will begin out- putting the identification data on the so pin during the subsequent cloc k cycles. the first byte that will be output will be the manufacturer id followed by two bytes of device id information. the fourth byte ou tput will be the extended device informat ion string length, which will be 00h indicating that no extended device information fo llows. as indicated in the jedec standard, reading the extended device information string length and any subsequent data is optional. deasserting the cs pin will terminate the manufacturer a nd device id read operation and put the so pin into a high-i mpedance state. the cs pin can be deasserted at any time and does not require that a full byte of data be read. command byte 1 byte 2 byte 3 byte 4 power of two page size 3dh 2ah 80h a6h opcode byte 1 opcode byte 2 opcode byte 3 opcode byte 4 cs each transition represents 8 bits si or io 7 - io 0
26 3542n?dflash?2/2014 at45db642d 14.1 manufacturer and d evice id information note: based on jedec publication 106 (jep106), manufacturer id data can be comprised of any number of bytes. some manufacturers may have manufacturer id codes that are two, three or even four bytes long with the first byte(s) in the sequence being 7fh. a system sh ould detect code 7fh as a ?continuation code? and continue to read manufacturer id by tes. the first non-7fh byte would signify the last byte of manufacturer id data. for adesto (and some other manufacturers), the manufacturer id data is comprised of only one byte. 14.1.1 byte 1 ? manufacturer id hex value jedec assigned code bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1fh 0 0 0 1 1 1 1 1 manufacturer id 1fh = adesto 14.1.2 byte 2 ? device id (part 1) hex value family code density code bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 family code 001 = dataflash 28h 0 0 1 0 1 0 0 0 density code 01000 = 64-mbit 14.1.3 byte 3 ? device id (part 2) hex value mlc code product version code bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 slc code 000 = 1-bit/cell technology 00h 0 0 0 0 0 0 0 0 product version 00000 = initial version 14.1.4 byte 4 ? extended device information string length hex value byte count bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00h 0 0 0 0 0 0 0 0 byte count 00h = 0 bytes of information 9fh manufacturer id byte n device id byte 1 device id byte 2 this information would only be output if the extended device information string length value was something other than 00h. extended device information string length extended device information byte x extended device information byte x + 1 cs 1fh 28h 00h 00h data data si so opcode each transition represents 8 bits
27 3542n?dflash?2/2014 at45db642d 14.2 operation m ode summary the commands described previously can be grouped into four different categories to better describe which commands can be executed at what times. group a commands consist of: 1. main memory page read 2. continuous array read 3. read sector protection register 4. read sector lockdown register 5. read security register group b commands consist of: 1. page erase 2. block erase 3. sector erase 4. chip erase 5. main memory page to buffer 1 (or 2) transfer 6. main memory page to buffer 1 (or 2) compare 7. buffer 1 (or 2) to main memory page program with built-in erase 8. buffer 1 (or 2) to main memory page program without built-in erase 9. main memory page program through buffer 1 (or 2) 10. auto page rewrite group c commands consist of: 1. buffer 1 (or 2) read 2. buffer 1 (or 2) write 3. status register read 4. manufacturer and device id read group d commands consist of: 1. erase sector protection register 2. program sector protection register 3. sector lockdown 4. program security register if a group a command is in progress (not fully completed), then another command in group a, b, c, or d should not be started. however, during the internally self-timed portion of group b commands, any command in group c can be executed. the group b commands using buffer 1 should use group c commands using buffer 2 and vi ce versa. finally, during the internally self- timed portion of a group d command, only the status register read command should be executed.
28 3542n?dflash?2/2014 at45db642d 15. command tables table 15-1. read commands command serial/8-bit opcode main memory page read both d2h continuous array read (legacy command) both e8h continuous array read (low frequency) serial 03h continuous array read serial 0bh buffer 1 read (low frequency) serial d1h buffer 2 read (low frequency) serial d3h buffer 1 read serial d4h buffer 2 read serial d6h buffer 1 read 8-bit 54h buffer 2 read 8-bit 56h table 15-2. program and erase commands command serial/8-bit opcode buffer 1 write both 84h buffer 2 write both 87h buffer 1 to main memory page program with built-in erase both 83h buffer 2 to main memory page program with built-in erase both 86h buffer 1 to main memory page program without built-in erase both 88h buffer 2 to main memory page program without built-in erase both 89h page erase both 81h block erase both 50h sector erase both 7ch chip erase both c7h, 94h, 80h, 9ah main memory page program through buffer 1 both 82h main memory page program through buffer 2 both 85h
29 3542n?dflash?2/2014 at45db642d table 15-3. protection and security commands command serial/8-bit opcode enable sector protection both 3dh + 2ah + 7fh + a9h disable sector protection both 3dh + 2ah + 7fh + 9ah erase sector protection register both 3dh + 2ah + 7fh + cfh program sector protection register 3dh + 2ah + 7fh + fch read sector protection register both 32h sector lockdown both 3dh + 2ah + 7fh + 30h read sector lockdown register both 35h program security register both 9bh + 00h + 00h + 00h read security register both 77h table 15-4. additional commands command serial/8-bit opcode main memory page to buffer 1 transfer both 53h main memory page to buffer 2 transfer both 55h main memory page to buffer 1 compare both 60h main memory page to buffer 2 compare both 61h auto page rewrite through buffer 1 both 58h auto page rewrite through buffer 2 both 59h deep power-down both b9h resume from deep power-down both abh status register read both d7h manufacturer and device id read serial 9fh
30 3542n?dflash?2/2014 at45db642d notes: x = don?t care a = address bit *the number with (*) is for 8-bit interface table 15-5. detailed bit-level addressing sequence for binary page size (1024-bytes) page size = 1024-bytes address byte address byte address byte additional don?t care bytes* opcode opcode 03h 00000011 x aaaaaaa aaaaaaaa aaaaaaaa n/a 0bh 00001011 x aaaaaaa aaaaaaaa aaaaaaaa 1 50h 01010000 x aaaaaaa aaax xxxx xxxxxxx x n/a 53h 01010011 x aaaaaaa aaaaaax x x x x xxxx x n/a 54h 01010100 x xxxxxxx xxxxxxaa aaa aaaaa 2* 55h 01010101 x aaaaaaa aaaaaax x x x x xxxx x n/a 56h 01010110 x xxxxxxx xxxxxxaa aaa aaaaa 2* 58h 01011000 x aaaaaaa aaaaaax x x x x xxxx x n/a 59h 01011001 x aaaaaaa aaaaaax x x x x xxxx x n/a 60h 01100000 x aaaaaaa aaaaaax x x x x xxxx x n/a 61h 01100001 x aaaaaaa aaaaaax x x x x xxxx x n/a 77h 01110111 x xxxxxxx xxxxxxxx xxxxxxx x 0 or 4* 7ch 01111100 x aaaaax x xxxxxxxx xxxxxxx x n/a 81h 10000001 x aaaaaaa aaaaaax x x x x xxxx x n/a 82h 10000010 x aaaaaaa aaaaaaaa aaaaaaaa n/a 83h 10000011 x aaaaaaa aaaaaax x x x x xxxx x n/a 84h 10000100 x xxxxxxx xxxxxxaa aaa aaaaa n/a 85h 10000101 x aaaaaaa aaaaaaaa aaaaaaaa n/a 86h 10000110 x aaaaaaa aaaaaax x x x x xxxx x n/a 87h 10000111 x xxxxxxx xxxxxxaa aaa aaaaa n/a 88h 10001000 x aaaaaaa aaaaaax x x x x xxxx x n/a 89h 10001001 x aaaaaaa aaaaaax x x x x xxxx x n/a 9fh 10011111 n/a n/a n/a n/a b9h 10111001 n/a n/a n/a n/a abh 10101011 n/a n/a n/a n/a d1h 11010001 x xxxxxxx xxxxxxaa aaa aaaaa n/a d2h 11010010 x aaaaaaa aaaaaaaa aaaaaaaa 4 or 19* d3h 11010011 x xxxxxxx xxxxxxaa aaa aaaaa n/a d4h 11010100 x xxxxxxx xxxxxxaa aaa aaaaa 1 d6h 11010110 x xxxxxxx xxxxxxaa aaa aaaaa 1 d7h 11010111 n/a n/a n/a 2* e8h 11101000 x aaaaaaa aaaaaaaa aaaaaaaa 4 or 19* a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0
31 3542n?dflash?2/2014 at45db642d note: p = page address bit b = byte/buffer address bitx = don?t care *the number with (*) is for 8-bit interface table 15-6. detailed bit-level addressing sequence for standard dataflash page size (1056-bytes) page size = 1056-bytes address byte address byte address byte additional don?t care bytes* opcode opcode 03h 0 0 0 0 0 0 1 1 pppppppp pppppbbb bbbbbbbb n/a 0bh 0 0 0 0 1 0 1 1 pppppppp pppppbbb bbbbbbbb 1 50h 0 1 0 1 0 0 0 0 pppppppp ppx x x x x x x x x x x x x x n/a 53h 0 1 0 1 0 0 1 1 pppppppp pppppx x x x x x x x x x x n/a 54h 01010100 xxxxxxxx xxxxxbbb bbbbbbbb 2* 55h 0 1 0 1 0 1 0 1 pppppppp pppppx x x x x x x x x x x n/a 56h 01010110 xxxxxxxx xxxxxbbb bbbbbbbb 2* 58h 0 1 0 1 1 0 0 0 pppppppp pppppx x x x x x x x x x x n/a 59h 0 1 0 1 1 0 0 1 pppppppp pppppx x x x x x x x x x x n/a 60h 0 1 1 0 0 0 0 0 pppppppp pppppx x x x x x x x x x x n/a 61h 0 1 1 0 0 0 0 1 pppppppp pppppx x x x x x x x x x x n/a 77h 01110111 xxxxxxxx xxxxxxxx xxxxxxxx 0 or 4* 7ch 01111100 pppppxxx xxxxxxxx xxxxxxx x n/a 81h 1 0 0 0 0 0 0 1 pppppppp pppppx x x x x x x x x x x n/a 82h 1 0 0 0 0 0 1 0 pppppppp pppppbbb bbbbbbbb n/a 83h 1 0 0 0 0 0 1 1 pppppppp pppppx x x x x x x x x x x n/a 84h 10000100 xxxxxxxx xxxxxbbb bbbbbbbb n/a 85h 1 0 0 0 0 1 0 1 pppppppp pppppbbb bbbbbbbb n/a 86h 1 0 0 0 0 1 1 0 pppppppp pppppx x x x x x x x x x x n/a 87h 10000111 xxxxxxxx xxxxxbbb bbbbbbbb n/a 88h 1 0 0 0 1 0 0 0 pppppppp pppppx x x x x x x x x x x n/a 89h 1 0 0 0 1 0 0 1 pppppppp pppppx x x x x x x x x x x n/a 9fh 10011111 n/a n/a n/a n/a b9h 10111001 n/a n/a n/a n/a abh 10101011 n/a n/a n/a n/a d1h 11010001 xxxxxxxx xxxxxbbb bbbbbbbb n/a d2h 1 1 0 1 0 0 1 0 pppppppp pppppbbb bbbbbbbb 4 or 19* d3h 11010001 xxxxxxxx xxxxxbbb bbbbbbbb n/a d4h 11010100 xxxxxxxx xxxxxbbb bbbbbbbb 1 d6h 11010110 xxxxxxxx xxxxxbbb bbbbbbbb 1 d7h 11010111 n/a n/a n/a 2* e8h 1 1 1 0 1 0 0 0 pppppppp pppppbbb bbbbbbbb 4 or 19* pa12 pa11 pa 10 pa9 pa8 pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 ba10 ba9 ba8 ba7 ba6 ba5 ba4 ba3 ba2 ba1 ba0
32 3542n?dflash?2/2014 at45db642d 16. power-on/reset state when power is first applied to the device, or when recovering from a reset condition, the device will default to mode 3. in additi on, the output pins (so or i/o 7 - i/o0) will be in a high impedance state, and a high-to-low transition on the cs pin will be required to star t a valid instruction. the mode (mode 3 or mode 0) will be automatically selected on every falling edge of cs by sampling the inactive clock state. 16.1 initial power-up/rese t timing restrictions at power up, the device must not be select ed until the supply voltage reaches the v cc (min.) and further delay of t vcsl . during power-up, the internal power-on reset circuitry keeps the device in reset mode until the v cc rises above the power-on reset threshold value (v por ). at this time, all operations are disabled and the device does not respond to any commands. after power up is applied and the v cc is at the minimum operating voltage v cc (min.), the t vcsl delay is required before the device can be selected in order to perform a read operation. similarly, the t puw delay is required after the v cc rises above the power-on reset threshold value (v por ) before the device can perform a write (pro gram or erase) operation. after initial power-up, the device will de fault in standby mode. table 16-1. initial power-up/reset timing restrictions 17. system considerations the rapids serial interface is controlled by the clock sck, serial input si and chip select cs pins. the sequential 8-bit rapid8 is controlled by the clock clk, eight i/os and chip select cs pins. these signals must rise and fall monotonica lly and be free from noise. excessive noise or ringing on these pins can be mi sinterpreted as multiple e dges and cause improper operation of the device. the pc board traces must be kept to a minimum distance or appropriately termi- nated to ensure proper operation. if necessa ry, decoupling capacitors can be added on these pins to provide filtering against noise glitches. as system complexity continues to increase, voltage regulation is becoming more important. a key element of any voltage regulation scheme is its current sourcing capability. like all flash memories, the peak current for dataflash occur during the programming and erase operation. the regulator needs to supply this peak current requirement. an under specified regulator can cause current starvation. besides increasing system noise, curr ent starvation during program- ming or erase can lead to improper operation and possible data corruption. the device uses an adaptive algorithm during pr ogram and erase operations. in order to opti- mize the erase and program time, use the rdy/busy bit of the status register or the rdy/busy pin to determine whether the program or erase operation was completed. fixed tim- ing is not recommended. symbol parameter min typ max units t vcsl v cc (min.) to chip select low 50 s t puw power-up device delay before write allowed 20 ms v por power-on reset voltage 1.5 2.5 v
33 3542n?dflash?2/2014 at45db642d 18. electrical specifications table 18-1. absolute maximum ratings* temperature under bias ................................ -55 ? c to +125 ? c *notice: stresses beyond thos e listed under ?absolute maximum ratings? may cause permanent dam- age to the device. the "absolute maximum rat- ings" are stress ratings only and functional operation of the device at these or any other con- ditions beyond those indicated in the operational sections of this specificat ion is not implied. expo- sure to absolute maximum rating conditions for extended periods may af fect device reliability. voltage extremes referenced in the "absolute maximum ratings" are intended to accommo- date short duration undershoot/overshoot condi- tions and does not imply or guarantee functional device operation at these levels for any extended period of time storage temperature ........ ........... ............ ..... -65 ? c to +150 ? c all input voltages (except v cc but including nc pins) with respect to ground ...................................-0.6v to +6.25v all output voltages with respect to ground .............................-0.6v to v cc + 0.6v table 18-2. dc and ac operating range at45db642d operating temperature (case) ind. -40 ? c to 85 ? c v cc power supply 2.7v to 3.6v
34 3542n?dflash?2/2014 at45db642d notes: 1. ai cc1 and i cc2 during a buffer read is 25ma maximum 2. all inputs (si, sck, cs#, wp#, and reset#) ar e guaranteed by design to be 5-volt tolerant table 18-3. dc characteristics symbol parameter condition min typ max units i dp deep power-down current cs , reset , wp = v ih , all inputs at cmos levels 15 25 a i sb standby current cs , reset , wp = v ih , all inputs at cmos levels 25 50 a i cc1 (1) active current, read operation, serial interface f = 33mhz; i out = 0ma; v cc = 3.6v 10 15 ma i cc2 (1) active current, read operation, rapid8 interface f = 33mhz; i out = 0ma; v cc = 3.6v 10 15 ma i cc3 active current, program operation, page program v cc = 3.6v 25 ma i cc4 active current, page erase, block erase, sector erase operation v cc = 3.6v 25 ma i li input load current v in = cmos levels 1 a i lo output leakage current v i/o = cmos levels 1 a v il input low voltage v cc x 0.3 v v ih input high voltage v cc x 0.7 v v ol output low voltage i ol = 1.6ma; v cc = 2.7v 0.4 v v oh output high voltage i oh = -100a v cc - 0.2v v
35 3542n?dflash?2/2014 at45db642d note: 1. values are based on device characterization, not 100% tested in production table 18-4. ac characteristics ? ra pids/serial interface symbol parameter min typ max units f sck sck frequency 66 mhz f car1 sck frequency for continuous array read 66 mhz f car2 sck frequency for continuous array read (low frequency) 33 mhz t wh sck high time 6.8 ns t wl sck low time 6.8 ns t sckr (1) sck rise time, peak-to-pe ak (slew rate) 0.1 v/ns t sckf (1) sck fall time, peak-to-peak (slew rate) 0.1 v/ns t cs minimum cs high time 50 ns t css cs setup time 5 ns t csh cs hold time 5 ns t csb cs high to rdy/busy low 100 ns t su data in setup time 2 ns t h data in hold time 3 ns t ho output hold time 0 ns t dis output disable time 27 35 ns t v output valid 6ns t wpe wp low to protection enabled 1 s t wpd wp high to protection disabled 1 s t edpd cs high to deep power-down mode 3 s t rdpd cs high to standby mode 35 s t xfr page to buffer transfer time 400 s t comp page to buffer compare time 400 s t ep page erase and programming time (1,024-/1,056-bytes) 17 40 ms t p page programming time (1,024-/1,056-bytes) 3 6 ms t pe page erase time (1,024-/1,056-bytes) 15 35 ms t be block erase time (8,192-/8,448-bytes) 45 100 ms t se sector erase time (262, 144-/270,336-bytes) 0.7 1.3 s t ce chip erase time tbd tbd s t rst reset pulse width 10 s t rec reset recovery time 1s
36 3542n?dflash?2/2014 at45db642d note: values are based on device characterization, not 100% tested in production table 18-5. ac characteristics ? rapid8 8-bit interface symbol parameter min typ max units f sck1 clk frequency 50 mhz f car1 clk frequency for continuous array read 50 mhz t wh clk high time 9 ns t wl clk low time 9 ns t clkr (1) clk rise time, peak-to-peak (slew rate) 0.1 v/ns t clkf (1) clk fall time, peak-to- peak (slew rate) 0.1 v/ns t cs minimum cs high time 50 ns t css cs setup time 5 ns t csh cs hold time 5 ns t csb cs high to rdy/busy low 100 ns t su data in setup time 2 ns t h data in hold time 5 ns t ho output hold time 0 ns t dis output disable time 12 ns t v output valid 12 ns t wpe wp low to protection enabled 1 s t wpd wp high to protection disabled 1 s t edpd cs high to deep power-down mode 3 s t rdpd cs high to standby mode 35 s t xfr page to buffer transfer time 400 s t comp page to buffer compare time 400 s t ep page erase and programming time (1,024-/1,056-bytes) 17 40 ms t p page programming time (1,024-/1,056-bytes) 3 6 ms t pe page erase time (1,024-/1,056-bytes) 15 35 ms t be block erase time (8,192-/8,448-bytes) 45 100 ms t se sector erase time (262,144-/270,336-bytes) 1.6 5 s t rst reset pulse width 10 s t rec reset recovery time 1 s
37 3542n?dflash?2/2014 at45db642d 19. input test waveforms and measurement levels t r , t f < 2ns (10% to 90%) 20. output test load 21. ac waveforms six different timing waveforms are shown below. waveform 1 shows the sck/clk signal being low when cs makes a high-to-low transition, and waveform 2 shows the sck/clk signal being high when cs makes a high-to-low transition. in both cases, output so becomes valid while the sck/clk signal is still low (sck/clk low time is specified as t wl ). timing waveforms 1 and 2 conform to rapids serial interface but for frequencies up to 66mhz. waveforms 1 and 2 are compatible with spi mode 0 and spi mode 3, respectively. waveform 3 and waveform 4 illustra te general timing diagram for r apids serial interface. these are similar to waveform 1 and waveform 2, except that output so is not restricted to become valid during the t wl period. these timing waveforms are valid over the full frequency range (max- imum frequency = 66mhz) of the rapids serial case. waveform 5 and waveform 6 are for 8-bit rapid8 interface over the full frequency range of operation (maximum frequency = 50mhz). 21.1 waveform 1 ? spi mode 0 compatible (for frequencies up to 66mhz) ac dri v i n g le v els ac measureme n t le v el 0.45 v 1.5 v 2.4 v device under test 30pf cs sck/clk si so t css v alid i n t h t su t w h t w l t csh t cs t v high impeda n ce v alid out t ho t dis high impeda n ce
38 3542n?dflash?2/2014 at45db642d 21.2 waveform 2 ? spi mode 3 compatible (for frequencies up to 66mhz) note: to operate the device at 50mhz in spi mode, the combined cpu setup time and rise/fall time should be less than 2ns 21.3 waveform 3 ? rapids mode 0 (f max = 66mhz) 21.4 waveform 4 ? rapids mode 3 (f max = 66mhz) 21.5 waveform 5 ? rapid8 mode 0 (f max = 50mhz) cs sck/clk so t css v alid i n t h t su t w l t w h t csh t cs t v high z v alid out t ho t dis high impeda n ce si cs sck/clk si so t css v alid i n t h t su t w h t w l t csh t cs t v high impeda n ce v alid out t ho t dis high impeda n ce cs sck/clk so t css v alid i n t h t su t w l t w h t csh t cs t v high z v alid out t ho t dis high impeda n ce si cs sck/clk i/o7 - i/o0 (i n put) i/o7 - i/o0 (output) t css v alid i n t h t su t w h t w l t csh t cs t v high impeda n ce v alid out t ho t dis high impeda n ce
39 3542n?dflash?2/2014 at45db642d 21.6 waveform 6 ? rapid8 mode 3 (f max = 50mhz) 21.7 utilizing the rapids function to take advantage of the rapids function's abili ty to operate at higher clock frequencies, a full clock cycle must be used to tran smit data back and forth across the serial bus. the dataflash is designed to always clock its data out on the falling edge of the sck signal and clock data in on the rising edge of sck. for full clock cycle operation to be achieved, when the dataflash is clocking data out on the fall- ing edge of sck, the host controller should wait until the next falling edge of sck to latch the data in. similarly, the host controller should clock its data out on the rising edge of sck in order to give the dataflash a full clock cycle to latc h the incoming data in on the next rising edge of sck. figure 21-1. rapids mode cs sck/clk i/o7 - i/o0 (output) t css v alid i n t h t su t w l t w h t csh t cs t v high z v alid out t ho t dis high impeda n ce i/o7 - i/o0 (i n put) sck mosi miso 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 mosi = master out, slave in miso = master in, slave out the master is the host controller and the slave is the dataflash the master always clocks data out on the rising edge of sck and always clocks data in on the falling edge of sck. the slave always clocks data out on the falling edge of sck and always clocks data in on the rising edge of sck. a. master clocks out first bit of byte-mosi on the rising edge of sck b. slave clocks in first bit of byte-mosi on the next rising edge of sck c. master clocks out second bit of byte-mosi on the same rising edge of sck d. last bit of byte-mosi is clocked out from the master e. last bit of byte-mosi is clocked into the slave f. slave clocks out first bit of byte-so g. master clocks in first bit of byte-so h. slave clocks out second bit of byte-so i. master clocks in last bit of byte-so a b c d e f g 1 h byte-mosi msb lsb byte-so msb lsb slave cs i
40 3542n?dflash?2/2014 at45db642d 21.8 utilizing the rapid8 function the rapid8 functions like rapids but with 8-bits of data inst ead of 1-bit. a full clock cycle must be used to transmit data back and forth across the 8-bit bus. the dataflash is designed to always clock its data out on the falling edge of the sck signal an d clock data in on the rising edge of sck. for full clock cycle operation to be achieved, when the dataflash is clocking data out on the fall- ing edge of sck, the host controller should wait until the next falling edge of sck to latch the data in. similarly, the host controller should clock its data out on the rising edge of sck in order to give the dataflash a full clock cycle to latc h the incoming data in on the next rising edge of sck. figure 21-2. rapid8 mode 21.9 reset timing note: the cs signal should be in th e high state before the reset signal is deasserted sck i/o 7-0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mosi = master out, slave in miso = master in, slave out the master would be the asic/mcu and the slave would be the memory device. the master always clocks data out on the rising edge of sck and always clocks data in on the falling edge of sck. the slave always clocks data out on the falling edge of sck and always clocks data in on the rising edge of sck. a. master clocks out byte 1 on the rising edge of sck b. slave clocks in byte 1 on the next rising edge of sck c. master clocks out byte 2 on the same rising edge of sck d. slave clocks in byte 6 (last input byte) e. slave clocks out byte a (first output byte) f. master clocks in byte a g. master clocks in byte h (last output byte) a b c d e f g slave cs byte 6 byte 5 byte 4 byte 3 byte 2 byte 1 byte a byte b byte c byte d byte e byte f byte g byte h t v cs sck/clk reset so or i/o7 - i/o0 (output) high impeda n ce high impeda n ce si or i/o7 - i/o0 (i n put) t rst t rec t css
41 3542n?dflash?2/2014 at45db642d 21.10 command sequence for read/write operations for page size 1024-bytes (except status register read, manufactur er and device id read) 21.11 command sequence for read/write operations for page size 1056-bytes (except status register read, manufactur er and device id read) 22. write operations the following block diagram and waveforms illustra te the various write sequences available. si or i/o7 - i/o0 (input)? cmd 8 bits 8 bits 8 bits page address (a22 - a10) x x x x x x x x x x x x x x x lsb x x x x x x x x byte/buffer address (a9 - a0/bfa9 - bfa0) msb si or i/o7 - i/o0 (input)? cmd 8 bits 8 bits 8 bits msb page address (pa12 - pa0) x x x x x x x x x x x x x x x x lsb x x x x x x x x byte/buffer address (ba10 - ba0/bfa10 - bfa0) flash memory array page (1024-/1056-bytes) buffer 2 (1024-/1056-bytes) buffer 1 (1024-/1056-bytes) i/o interface si buffer 1 to main memory page program buffer 2 to main memory page program buffer 1 write buffer 2 write i/o7 - i/o0
42 3542n?dflash?2/2014 at45db642d 22.1 buffer write 22.2 buffer to main memory page program (dat a from buffer program med into flash page) 23. read operations the following block diagram and waveforms illustra te the various read sequences available. si or i/o7 - i/o0 (input) cmd completes writing into selected buffer cs x xx, bfa10-8 bfa7-0 n n+1 last byte binary page size 14 don't care + bfa9-bfa0 si or i/o7 - i/o0 (input) cmd pa12-5 pa4-0, xxx cs starts self-timed erase/program operation xxxx xx each transition represents 8 bits n = 1st byte read n+1 = 2nd byte read binary page size a22-a10 + 10 don't care bits flash memory array page (1024-/1056-bytes) buffer 2 (1024-/1056-bytes) buffer 1 (1024-/1056-bytes) i/o interface main memory page to buffer 1 main memory page to buffer 2 main memory page read buffer 1 read buffer 2 read so i/o7 - i/o0
43 3542n?dflash?2/2014 at45db642d 23.1 main memory page read 23.2 main memory page to buff er transfer (data from flash page read into buffer) 23.3 buffer read si or i/o7 - i/o0 (input) cmd pa12-5, pa4-0 ba10-8 x cs n n+1 so or i/o7 - i/o0 (output) ba7-0 4 dummy bytes for serial 19 dummy bytes for parallel x address for binary page size a22-a16 a15-a8 a7-a0 starts reading page data into buffer si or i/o7 - i/o0 (input) cmd pa12-5 pa4-0, xxx cs so or i/o7 - i/o0 (output) xxxx xxxx binary page size a22-a10 + 10 don't care bits cmd cs n n+1 x x no dummy byte (serial, opcodes d1h and d3h) 1 dummy byte (serial, opcodes d4h and d6h) 2 dummy bytes (parallel) x..x, bfa10-8 bfa7- 0 binary page size 14 don't care + bfa9-bfa0 each transition represents 8 bits si or io 7 - io 0 so or io 7 - io 0
44 3542n?dflash?2/2014 at45db642d 24. detailed bit-level read waveform ? rapids serial interf ace mode 0/mode 3 24.1 continuous array read (legacy opcode e8h) 24.2 continuous array read (opcode 0bh) 24.3 continuous array read (low frequency: opcode 03h) sck cs si so msb msb 23 1 0 11101000 67 5 41011 9 812 636667 65 64 62 33 34 31 32 29 30 68 71 72 70 69 opcode aaaa aaa aa msb xxxx xx msb msb dddddddd d d address bits 32 don't care bits data byte 1 high-impedance bit 8191/8447 of page n bit 0 of page n+1 sck cs si so msb msb 23 1 0 00001011 67 5 41011 9 812 394243 41 40 38 33 34 31 32 29 30 44 47 48 46 45 opcode aaaa aaa aa msb xxxx xx msb msb dddddddd d d address bits a23 - a0 don't care data byte 1 high-impedance 36 37 35 x x sck cs si so msb msb 23 1 0 00000011 67 5 41011 9 812 3738 33 36 35 34 31 32 29 30 39 40 opcode aaaa aaa aa msb msb dddddddd d d address bits a23-a0 data byte 1 high-impedance
45 3542n?dflash?2/2014 at45db642d 24.4 main memory page read (opcode: d2h) 24.5 buffer read (opcode d4h or d6h) 24.6 buffer read (low freque ncy: opcode d1h or d3h) sck cs si so msb msb 23 1 0 11010010 67 5 41011 9 812 636667 65 64 62 33 34 31 32 29 30 68 71 72 70 69 opcode aaaa aaa aa msb xxxx xx msb msb dddddddd d d address bits 32 don't care bits data byte 1 high-impedance sck cs si so msb msb 2 3 1 0 1 1 0 1 0 1 0 0 6 7 5 4 10 11 9 8 12 39 42 43 41 40 37 38 33 36 35 34 31 32 29 30 44 47 48 46 45 opcode x x x x a a a x x msb x x x x x x x x msb msb d d d d d d d d d d address bits binary page size = 14 don't care + bfa9-bfa0 standard dataflash page size = 13 don't care + bfa10-bfa0 don't care data byte 1 high-impedance sck cs si so msb msb 2 3 1 0 1 1 0 1 0 0 0 1 6 7 5 4 10 11 9 8 12 37 38 33 36 35 34 31 32 29 30 39 40 opcode x x x x a a a x x msb msb d d d d d d d d d d data byte 1 high-impedance address bits binary page size = 14 don't care + bfa9-bfa0 standard dataflash page size = 13 don't care + bfa10-bfa0
46 3542n?dflash?2/2014 at45db642d 24.7 read sector protecti on register (opcode 32h) 24.8 read sector lockdown register (opcode 35h) 24.9 read security re gister (opcode 77h) sck cs si so msb msb 23 1 0 00110010 67 5 41011 9 812 3738 33 36 35 34 31 32 29 30 39 40 opcode xxxx xxx xx msb msb ddddddd d d don't care data byte 1 high-impedance sck cs si so msb msb 23 1 0 00110101 67 5 41011 9 812 3738 33 36 35 34 31 32 29 30 39 40 opcode xxxx xxx xx msb msb ddddddd d d don't care data byte 1 high-impedance sck cs si so msb msb 23 1 0 01110111 67 5 41011 9 812 3738 33 36 35 34 31 32 29 30 39 40 opcode xxxx xxx xx msb msb ddddddd d d don't care data byte 1 high-impedance
47 3542n?dflash?2/2014 at45db642d 24.10 status register read (opcode d7h) 24.11 manufacturer and device read (opcode 9fh) sck cs si so msb 23 1 0 11010111 67 5 41011 9 812 2122 17 20 19 18 15 16 13 14 23 24 opcode msb msb dddddd dd d d msb dddddd d d status register data status register data high-impedance sck cs si so 6 0 9fh 8 7 38 opcode 1fh device id byte 1 device id byte 2 00h high-impedance 14 16 15 22 24 23 30 32 31 note: each transition shown for si and so represents one byte (8 bits)
48 3542n?dflash?2/2014 at45db642d 25. detailed 8-bit read wavefo rms ? rapid8 mode 0/mode 3 25.1 continuous array read (opcode: e8h) 25.2 main memory page read (opcode: d2h) 25.3 buffer read (opcode: 54h or 56h) i/o7-i/o0 (input) x x x cs i/o7-i/o0 (output) clk 21 22 23 24 25 high impedance data data data data data data data data data byte 0 of page n+1 byte 1023/1055 of page n t v data out cmd addr addr addr 1 2 3 0 binary & standard dataflash page size t su 26 19 dummy bytes i/07-i/o0 (input) cmd addr addr addr x x x cs i/07-i/o0 (output) clk 1 2 3 0 20 21 22 23 24 25 26 x x high impedance data data data data out t su t v data 19 19 dummy bytes binary & standard dataflash page size i/o7-i/o0 (input) cmd x addr addr cs i/o7-i/o0 (output) clk 1 2 3 4 5 6 7 0 high impedance data data data data out t su t v x x address bytes dummy bytes binary & standard dataflash page size
49 3542n?dflash?2/2014 at45db642d 25.4 status register read (opcode: d7h) 26. auto page rewrite flowchart figure 26-1. algorithm for programming or reprogramming of the entire array sequentially notes: 1. this type of algorithm is used for applications in which the entire array is programmed sequentially, filling the array page-by- page. 2. a page can be written using either a main memory page prog ram operation or a buffer writ e operation followed by a buffer to main memory page program operation. 3. the algorithm above shows the programming of a single page. the algorithm will be repeated sequentially for each page within the entire array. i/o7-i/o0 (input) cmd cs i/o7-i/o0 (output) clk 1 23 high impedance x xdata status register output t su t v data 0 start mai n memory page program through buffer ( 8 2h, 8 5h) e n d pro v ide address and data buffer w rite ( 8 4h, 8 7h) buffer to mai n memory page program ( 8 3h, 8 6h)
50 3542n?dflash?2/2014 at45db642d figure 26-2. algorithm for randomly modifying data notes: 1. to preserve data integrity, each page of an dataflash sector must be updated/rewritten at least once within every 10,00 0 cumulative page erase and program operations. 2. a page address pointer must be maintained to indicate whic h page is to be rewritten. t he auto page rewrite command must use the address specified by the page address pointer. 3. other algorithms can be used to rewrite po rtions of the flash array. low-power app lications may choose to wait until 10,000 cumulative page erase and program operations have accumulate d before rewriting all pages of the sector. see application note an-4 (?using adesto serial dataflash?) for more details. start mai n memory page to buffer tra n sfer (53h, 55h) i n creme n t page address poi n ter (2) auto page re w rite (2) (5 8 h, 59h) e n d pro v ide address of page to modify if planning to modify m u ltiple b ytes c u rrently stored w ithin a page of the flash array mai n memory page program through buffer ( 8 2h, 8 5h) buffer w rite ( 8 4h, 8 7h) buffer to mai n memory page program ( 8 3h, 8 6h)
51 3542n?dflash?2/2014 at45db642d 27. ordering information 27.1 ordering code detail notes: 1. the shipping carrier option is not marked on the devices 2. standard parts are shipped with the page size set to 1056-bytes . the user is able to configure these parts to a 1024-byte page size if desired 3. parts ordered with suffix sl954 are shipped in bulk with the page size set to 1024-bytes. parts will have a 954 or sl954 marked on them 4. parts ordered with suffix sl955 are sh ipped in tape and reel with the page size set to 1024-bytes. parts will have a 954 or sl954 marked on them at4 5d 6 4 cnu 2d? b designator product family device density 64 = 64-megabit interface 2 = dual package option cn = 8-lead, 6 x 8mm cason t = 28-lead, 8 x 13.4mm tsop device grade u = matte sn lead finish, industrial temperature range (-40c to +85c) device revision c = 24 ball bga 27.2 green package options (pb/ halide-free/rohs compliant) ordering code (1)(2) package lead finish operating voltage f sck (mhz) operation range AT45DB642D-CNU AT45DB642D-CNU-sl954 (3) AT45DB642D-CNU-sl955 (4) 8cn3 matte sn 2.7v to 3.6v 66 industrial (-40 ? c to 85 ? c) 2.7v to 3.6v at45db642d-tu 28t at45db642d-cu 24c1 matte sn 2.7v to 3.6v 66 package type 28t 28-lead, (8 x 13.4mm) plastic thin small outline package, type i (tsop) 8cn3 8-pad (6mm x 8mm) chip array small outline no lead package (cason) 24c1 24-ball, 6mm x 8mm x 1,4mm ball grid array with a 1mm pitch 5 x 5 ball matrix
52 3542n?dflash?2/2014 at45db642d 28. packaging information 28.1 28t ? tsop, type 1 title drawing no. rev. 28t , 28-lead (8 x 13.4mm) plastic thin small outline package, type i (tsop) c 28t 12/06/02 pin 1 0o ~ 5o d1 d pin 1 identifier area b e e a a1 a2 c l gage plane seating plane l1 common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference mo-183. 2. dimensions d1 and e do not include mold protrusion. allowable protrusion on e is 0.15mm per side and on d1 is 0.25mm per side. 3. lead coplanarity is 0.10mm maximum. a ? ? 1.20 a1 0.05 ? 0.15 a2 0.90 1.00 1.05 d 13.20 13.40 13.60 d1 11.70 11.80 11.90 note 2 e 7.90 8.00 8.10 note 2 l 0.50 0.60 0.70 l1 0.25 basic b 0.17 0.22 0.27 c 0.10 ? 0.21 e 0.55 basic package drawing contact: contact@adestotech.com
53 3542n?dflash?2/2014 at45db642d 28.2 8cn3 ? cason title drawing no. rev. package drawing contact: contact@adestotech.com 8cn3, 8-pad (6 x 8 x 1.0mm body), lead pitch 1.27mm, chip array small outline no lead package (cason) b 8cn3 7/10/03 notes: 1. all dimensions and tolerance conform to asme y 14.5m, 1994 2. the surface finish of the package shall be edm charmille #24-27 3. unless otherwise specified tolerance: decimal 0.05, angular 2 o 4. metal pad dimensions common dimensions (unit of measure = mm) symbol min nom max note a 1.0 a1 0.17 0.21 0.25 b 0.41 typ 4 d 7.90 8.00 8.10 e 5.90 6.00 6.10 e 1.27 bsc e1 1.095 ref l 0.67 typ 4 l1 0.92 0.97 1.02 4 pin1 pad corner marked pin1 indentifier 0.10 mm typ 4 3 2 1 5 6 7 8 top view l b e l1 e1 side view a1 a bottom view e d
54 3542n?dflash?2/2014 at45db642d 28.3 24c1 - ball grid array title drawing no. rev. package drawing contact: contact@adestotech.com 24c1 , 24-ball (5 x 5 array), 6 x 8 x 1.4 mm body, 1.0 mm ball pitch chip-scale ball grid array package (cbga) a 24c1 04/11/01 dimensions in millimeters and (inches). controlling dimension: millimeters. a b c d e 54321 4.0 (0.157) 1.00 (0.039) ref 0.46 (0.018) dia ball typ 2.00 (0.079) ref 4.0 (0.157) 8.10(0.319) 7.90(0.311) 1.40 (0.055) max 0.30 (0.012)min 6.10(0.240) 5.90(0.232) 1.00 (0.0394) bsc non-accumulative a1 id 1.00 (0.0394) bsc non-accumulative top view side view bottom view
55 3542n?dflash?2/2014 at45db642d 29. revision history revision level ? release date history a ? september 2005 initial release b ? november 2005 changed t vcsl from 30s to 50s min. changed t puw from 10ms to 20ms max. changed t dis from 8ns to 6ns max. changed t v from 8ns to 6ns max. c ? march 2006 added text, in ?programming the conf iguration register?, to indicate that power cycling is required to s witch to ?power of 2? page size after the opcode has been executed. d ? july 2006 corrected typographical errors. e ? august 2006 added errata regarding chip erase. f ? august 2006 added t sckr and t sckf parameters to table 18-4. g ? august 2007 added additional text for ?power of 2? binary page size option. changed t rdpd from 30s to 35s. added t clkr and t clkf parameters to table 18-5. h ? april 2008 added part number ordering code details for suffixes sl954/955. added ordering code details. i ? february 2009 changed t dis (typ and max) to 27ns and 35ns, respectively, for rapids interface. j ? march 2009 changed deep power-down current values - increased typical value from 9a to 15a. - increased maximum value from 18a to 25a. k ? april 2009 updated absolute maximum ratings added 24c1 24 ball bga package option deleted dataflash card package option l ? may 2010 changed t se (typ) 1.6 to 0.7 and (max) 5 to 1.3 changed from 10,000 to 20,000 cumulative page erase/program operations and added the please contact adesto statement in section 11.3 . m-november 2012 update all adesto logos. n- february 2014 not recommended for new designs.
56 3542n?dflash?2/2014 at45db642d 30. errata 30.1 chip erase 30.1.1 issue in a certain percentage of units, the chip er ase feature may not function correctly and may adversely affect device operation. therefore, it is recommended that the chip erase commands (opcodes c7h, 94h, 80h, and 9ah) not be used. 30.1.2 workaround use block erase (opcode 50h) as an alternative. the block erase function is not affected by the chip erase issue. 30.1.3 resolution the chip erase feature may be fixed with a new revision of the device. please contact adesto ? for the estimated availability of devices with the fix.
corporate office california | usa adesto headquarters 1250 borregas avenue sunnyvale, ca 94089 phone: (+1) 408.400.0578 email: contact@adestotech.com ? 2014 adesto technologies. all rights reserved. / rev.: 3542n?dflash?2/2014 disclaimer: adesto technologies corporation makes no warranty for the use of its products, other than those expressly contained in the company's standard warranty which is detailed in adesto's terms and conditions located on the company's web site. the company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. no lic enses to patents or other intellectual property of adesto are granted by the company in connection with the sale of adesto products, expressly or by implication. adesto's products are not authorized for u se as critical components in life support devices or systems. adesto ? , the adesto logo, cbram ? , and dataflash ? are registered trademarks or trademarks of adesto technologies. all other marks are the property of their respective owners.

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